Embodiments of the present invention provide a multilevel cache system and method. In particular, the present invention relates to a cache system that has multiple cache hierarchies.
Many computer, systems use multiple levels of caches to cache data from a memory device. For example, a computer system may have a level one cache (L1) and a larger level two cache (L2), in addition to an even larger RAM memory. The L1 cache typically contains a copy of information that was previously loaded from RAM by the processor, and the L2 cache typically contains both a copy of information in the L1 cache and other information that had been loaded from RAM by the processor less recently than the information in the L1 cache.
Each of the caches in such computer systems contain a data array, which stores information copied from the memory, and a tag array, which stores a directory of the information that is contained in the corresponding data array. Using the example above, the system would have an L1 data array, an L1 tag array that contains a directory of information in the L1 data array, an L2 data array, and an L2 tag array that contains a directory of information in the L2 data array. In addition, many computer systems also have multiple translation lookaside buffers (TLB). The TLBs may be used to implement the virtual address system (e.g., to translate from virtual addresses to physical addresses) and to prevent programs from accessing protected areas of memory.
When the processor in the example system described above issues a memory load request, this request is broadcast to the L1 cache system, including the L1 TLB, L1 tag array, and L1 data array. The L1 tag array is examined to determine if the requested information is in the L1 data array. If the requested information is in the L1 data array, the information is returned from the L1 data array to the processor. If a search of the L1 tag array indicates that the information is not in the L1 cache, then a cache miss is forwarded to the L2 cache. This causes a request to be sent to the L2 tag array and L2 data array. If a search of the L2 tag array indicates that the requested information is in the L2 data array, the information is returned from the L2 data array to the processor. If such a search indicates that the requested information is not in the L2 data array, then the request is forwarded to the next level in the memory hierarchy, which may be another cache or may be the system RAM.